The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2003

Filed:

Sep. 30, 2002
Applicant:
Inventors:

Wei-Hua Cheng, Singapore, SG;

Daniel Yen, Singapore, SG;

Kunihiko Takahashi, Singapore, SG;

Ming Lei, Singapore, SG;

Thomas Joy, Singapore, SG;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/18242 ;
U.S. Cl.
CPC ...
H01L 2/18242 ;
Abstract

A method for making metal-insulator-metal (MIM) capacitors having insulators with high-dielectric-constant or ferroelectric interelectrode films compatible with the dual-damascene process is achieved. The method of integrating the MIM with a dual-damascene process is to form a planar a first insulating layer and to deposit an etch-stop layer and a second insulating layer. Capacitor node contact openings are etched to the substrate and first recesses are etched to the etch-stop layer. The contact openings and first recesses are filled with a conducting layer using a dual-damascene process. Second recesses are formed in the second insulating layer around the capacitor node contacts. A conformal first metal layer, an interelectrode dielectric layer, and a second metal layer are deposited, and are patterned at the same time to form the capacitors over the node contacts. The second recesses increase the capacitor area while the simultaneous patterning of the metal layers results in fewer processing steps.


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