The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2003

Filed:

Aug. 22, 2000
Applicant:
Inventors:

Yongzhong Hu, San Jose, CA (US);

Jein Chen Young, Milpitas, CA (US);

Stewart Logie, Campbell, CA (US);

Assignee:

Lattice Semiconductor Corporation, Hillsboro, OR (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/9788 ;
U.S. Cl.
CPC ...
H01L 2/9788 ;
Abstract

A non-volatile memory cell at least partially formed in a semiconductor substrate. The cell comprises a first transistor comprising a high voltage NMOS transistor having a first active region and a second active region; a second transistor sharing said second active region and having a third active region in said substrate; an active control gate region formed in said substrate; a polysilicon layer having a first portion forming a gate for said first transistor, and a second portion forming gate for said second transistor and a floating gate overlying said active control gate region. In one embodiment, an oxynitride separates said second portion and said active control gate region.


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