Apparatus and method for testing for defects between memory cells in packaged semiconductor memory devices

Abstract

A semiconductor memory device includes a die having a semiconductor memory circuit formed thereon and a plurality of pads at the periphery of the die that are electrically coupled to the circuit. Electrically conductive leads have a pin end for external coupling, and a free end electrically connected by bond wires to certain pads on the die. An encapsulating material such as epoxy encapsulates the die, bond wires and free ends of the leads to form a packaged chip. A superfluous lead such as a redundant voltage supply lead or non-connected lead is coupled, by means of a bond wire, to a pad that, in turn, is coupled to a voltage boosting circuit on the die. The voltage boosting circuit is coupled to row lines in the semiconductor memory circuit to provide boosted voltage thereto. External power can thereby be provided to the row lines, through the voltage boosting circuits, to simultaneously enable at least half of the row lines during stress testing of the chip. The arrangement allows for efficient testing for cell-to-cell defects while the die is in packaged chip form.