The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2003

Filed:

Jul. 23, 2001
Applicant:
Inventors:

Meng Huaug Liu, Hsinchu, TW;

Chun-Hsiang Lai, Taichung, TW;

Sing Su, Banchiau, TW;

Tao Cheng Lu, Kaohsiung, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02H 9/00 ;
U.S. Cl.
CPC ...
H02H 9/00 ;
Abstract

The present invention provides an IC ESD cell, which is applicable to multiple-power-input and mixed-voltage ICs and capable of maintaining power sequence independence of each power source. The ESD cell of the present invention comprises a voltage selector circuit, which connects two separate power sources to select the one having a higher potential as the output voltage. An NMOS is used to connect the two separate power sources. An RC circuit is connected to an output of the voltage selector circuit to distinguish ESD event from normal power source. Therefore, the channel of the NMOS will be conducted to let the ESD current be led out via a designed path, hence preventing internal circuits of an IC from damage and accomplishing the object of whole chip protection.


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