Method for making closely spaced capacitors with reduced parasitic capacitance on a dynamic random access memory (dram) device

Abstract

A method for making DRAM devices having reduced parasitic capacitance between closely spaced capacitors is achieved. After forming FETs for the memory cells and bit lines having bit-line contacts, a planar insulating layer is formed having an etch-stop layer thereon. Contact openings are etched in the insulating layer and are filled with polysilicon to make contact to capacitor node contact plugs. A relatively thick insulating layer having a low dielectric constant (k) is deposited, and an array of recesses are etched over the node contact plugs for crown-shaped capacitors. A polysilicon layer and an interelectrode dielectric layer are formed in the array of recesses, and another polysilicon layer is patterned to complete the crown capacitors. The low-k insulator between adjacent capacitors reduces the parasitic capacitance and improves data retention of DRAM cells. Alternatively, higher density of memory cells can be formed without increasing parasitic capacitance.