The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2003

Filed:

Apr. 26, 2002
Applicant:
Inventors:

Thomas M. Brown, Austin, TX (US);

Edward O. Travis, Austin, TX (US);

Jeffrey C. Haines, Austin, TX (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1302 ;
U.S. Cl.
CPC ...
H01L 2/1302 ;
Abstract

A model-based approach for generating an etch pattern to decrease topographical uniformity involves placing reverse dummy features ( ) in a region of a semiconductor substrate ( ) according to the topography of the region and adjacent regions. The reverse dummy features are placed inconsistently over the semiconductor substrate ( ) because the need for reverse dummy features is inconsistent and varies from design to design. In one embodiment, the reverse dummy features ( ) having varying widths are placed with varying spacing between them and are placed in different regions. The determination of location, size and spacing of the reverse dummy features ( ) is determined based upon the uniformity effect over the entire semiconductor die and may be used in conjunction with the placement of printed dummy features. After placing the reverse dummy features ( ), a planarization process may be performed to remove the reverse dummy features, which improves the planarization.


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