The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 26, 2003
Filed:
Dec. 21, 1999
Applicant:
Inventor:
Lawrence S. Uzelac, Auburn, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/32 ;
U.S. Cl.
CPC ...
G06F 1/32 ;
Abstract
A CMOS circuit for low leakage battery operation connects the real time clock to the power supply when available or to a low leakage source when the power supply is not available.
Quick Actions:
Uzelac, Lawrence. (2003). Method and apparatus for changing bias levels to reduce cmos leakage of a real time clock when switching to a battery mode of operation (U.S. Patent No. 6611918). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6611918
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