The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2003

Filed:

Oct. 07, 2002
Applicant:
Inventors:

Takao Akaogi, Kawasaki, JP;

Nobuaki Takashina, Kawasaki, JP;

Yasushi Kasa, Kawasaki, JP;

Kiyoshi Itano, Kawasaki, JP;

Hiromi Kawashima, Kawasaki, JP;

Minoru Yamashita, Kawasaki, JP;

Shouichi Kawamura, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 1/604 ;
U.S. Cl.
CPC ...
G11C 1/604 ;
Abstract

A semiconductor memory device has 2 word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2 (n>m) word lines among the 2 word lines, and a second unit for not selecting a block of 2 (m>k) word lines among the 2 word lines. The second unit does not select the block of 2 word lines, and selects a block of 2 word lines prepared outside the 2 word lines when any one of the 2 word lines among the 2 word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.


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