The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2003

Filed:

Mar. 23, 2001
Applicant:
Inventors:

Ronald A. Powell, San Carlos, CA (US);

Sridhar K. Kailasam, Santa Clara, CA (US);

E. Derryck Settles, Franklin, MA (US);

Larry R. Lane, San Jose, CA (US);

Assignee:

Novellus Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/144 ;
U.S. Cl.
CPC ...
H01L 2/144 ;
Abstract

The present invention pertains to systems and methods for simultaneously producing a diffusion barrier and a seed layer used in integrated circuit metallization. This is achieved by initially depositing copper-magnesium (Cu—Mg) alloys with relatively high levels of Mg (>10 atomic %, which is equivalent to about >4 weight %). After the alloys are deposited, they self-form a magnesium oxide (MgO) based barrier layer at the substrate interface, thus eliminating the need for a separate operation for barrier deposition. The migration of Mg to the substrate interface leaves the remainder of the film relatively pure Cu.


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