Wafer level stack chip package and method for manufacturing same

Abstract

A wafer level chip package has a redistrubution substrate, at least one lower semiconductor chip stacked on the redisctribution substrate, and an uppermost semiconductor chip. The redistribution substrate has a redistribution layer and substrate pads connected to the redistribution layer. The lower semiconductor chip is stacked on the redistribution layer and may have through holes for partially exposing the redistribution layer, the through holes corresponding to the substrate pads, and having conductive filling material filling the through holes. The uppermost semiconductor chip may have the same elements as the lower semiconductor chip, and may be flip chip bonded to the through holes. The package may further have a filling layer for filling areas between chips, a metal lid for coating most of the external surfaces, and external connection terminals formed on and electrically connected to the exposed redistribution layer from the first dielectric layer of the redistribution substrate.