The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 2003
Filed:
Jun. 01, 2000
Carl A. Vickery, Garland, TX (US);
James D. Goon, Dallas, TX (US);
Robert A. Tuerck, Garland, TX (US);
Troy M. Loveday, Allen, TX (US);
Jesse Rojas, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
The number of good IC (Integrated Circuit) chips per wafer or time to print a wafer is optimized by examining a number of prospective chip-to-wafer offsets, and, for each offset, a number of prospective arrangements of reticle exposures (shot maps). Integrating such a shot map optimization sub-system with a reticle layout (frame generation) sub-system permits creation of an optimal shot map for an IC chip of known size. These two sub-systems can also be used iteratively to explore a range of possible chip sizes, presenting the results in a simple graphical form. The instant invention integrates shot map optimization, frame generation and chip size optimization/visualization into a single system, providing the chip designer with insight into the impact of chip size on manufacturability.