The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2003

Filed:

Jul. 17, 2002
Applicant:
Inventors:

Byung-lyul Park, Seoul, KR;

Ju-hyuk Chung, Suwon, KR;

Ja-hyung Han, Suwon, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/18242 ; H01L 2/14763 ;
U.S. Cl.
CPC ...
H01L 2/18242 ; H01L 2/14763 ;
Abstract

A method for manufacturing a semiconductor device having a metal-insulator-metal (MIM) capacitor and a damascene wiring layer structure, wherein first and second metal wiring layers are formed in a lower dielectric layer on a semiconductor substrate such that top surfaces of the first and second metal wiring layers and the lower dielectric layer are level. First and second dielectric layers are sequentially formed to have a hole exposing the top surface of the second metal wiring layer. An upper electrode of a capacitor is formed in the hole region such that the top surfaces of the upper electrode and the second dielectric layer are level. Third and fourth dielectric layers are sequentially formed on the substrate. A damascene structure is formed to contact the top surface of the first metal wiring layer, and a contact plug is formed to contact the top surface of the upper electrode.


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