The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 22, 2003
Filed:
Oct. 22, 2001
Bin-Shing Chen, Hsinchu, TW;
Chiyeh Lo, Taipei, TW;
Winbond Electronics Corp., Hsinchu, TW;
Abstract
A method is used to form a flash reference memory cell and comprises the following steps. A floating well is formed in a substrate. A first dielectric layer is formed to cover the substrate. A defined floating gate is formed on the first dielectric layer and aligned with the floating well. A second dielectric layer is formed on the substrate. A contact window is formed by defining the second dielectric layer to expose portions of the floating gate. A heavy ion implantation is performed on the exposed floating gate. A third dielectric layer is formed to cover the substrate and fills the contact window. The well region in the substrate is used as the isolation between the floating gate and the substrate to prevent the problems of over-etching in the contact window process and misalignment in the floating gate process. The heavy ion implantation process increases the amount of the dopant in the floating gate to reduce the resistance of the floating gate window, to improve the RC delay of the flash reference memory cell, and further to enhance the operation speed of the device.