The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 2003
Filed:
Aug. 23, 2001
Approach to structurally reinforcing the mechanical performance of silicon level interconnect layers
Applicant:
Inventors:
Michael F. Chisholm, Garland, TX (US);
Darvin R. Edwards, Garland, TX (US);
Gregory B. Hotchkiss, Richardson, TX (US);
Reynaldo Rincon, Richardson, TX (US);
Viswanathan Sundararaman, Dallas, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/348 ;
U.S. Cl.
CPC ...
H01L 2/348 ;
Abstract
A conductive via pattern ( ) between the uppermost metal interconnect layer (M ) and next underlying metal interconnect layer (M ) in the bond pad areas strengthens the interlevel dielectric (ILD ) between metal layers (M and M ). The conductive via layer ( ) may, for example, comprise parallel rails ( ) or a grid of cross-hatch rails ( ). By spreading the stress concentration laterally, the conductive via layer ( ) inhibits micro-cracking from stress applied to the bond pad ( ).