Simple photo development step to form tisix gate in dram process

Abstract

A method of using resist planarization to prepare for silicidation while protecting silicon nitride spacers in the fabrication of integrated circuits is described. Field oxide areas are formed on a semiconductor substrate surrounding and electrically isolating a logic device area and a memory device area. Polysilicon gate electrodes having silicon nitride sidewall spacers and associated source/drain regions are formed in the device areas. A silicon oxide layer is deposited overlying the gate electrodes and source/drain regions. The silicon oxide layer is covered with a photoresist layer. The photoresist layer is developed until the silicon oxide layer overlying the gate electrodes is exposed and the photoresist layer is below the tops of the gate electrodes. The exposed silicon oxide layer is etched away whereby the tops of the gate electrodes are exposed and wherein the silicon nitride spacers are undamaged by the etching. All of the silicon oxide layer in the logic device area is etched away. A layer of titanium is deposited over the semiconductor substrate which is annealed to transform the titanium layer into a titanium silicide layer over the gate electrodes and over the source/drain regions in the logic area. The unreacted titanium layer is removed to leave the titanium silicide layer only on the top surface of the gate electrodes and on the top surface of the semiconductor substrate overlying the source/drain regions associated with the gate electrodes in the logic device area.