The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 24, 2003
Filed:
Sep. 21, 2000
Zohar Bogin, Folsom, CA (US);
Serafin E. Garcia, Folsom, CA (US);
Steven J. Clohset, San Francisco, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A technique to reduce accumulated latencies in bus transmission time when a bus inversion scheme is employed. The bus inversion scheme inverts all the data bits whenever more than one-half of the data bits are active, so that the bus never has more that one-half of the bits active during a data transfer. This minimizes the number of driver circuits that are actively driving the bus at any given time. Since it takes a certain amount to time to determine if more than one-half of the bits are active, this process can add to overall latency, or data transfer time on the bus. By placing the bus inversion function in parallel with another function that also contributes to bus latency, such as error correction code (ECC) calculation, only the more time-consuming of the two functions will increase bus latency.