Field effect transistors having elevated source/drain regions

Abstract

Field effect transistors (FETs) include an integrated circuit substrate having a surface, and a gate on the surface. A pair of recessed regions in the substrate are located beneath the surface. Respective ones of the recessed regions are located on respective opposite sides of the gate. Each of the recessed regions define a sidewall and a floor. An elevated source/drain structure on each of the recessed regions is at least as thick adjacent to the gate as remote from the gate. A gate spacer may be included between the gate and the elevated source/drain region. The gate spacer can comprise an insulating film. Preferably, the source/drain structure extends to the sidewall of the recessed region. The elevated source/drain structure is preferably free of a facet adjacent the gate. The present invention also relates to methods for fabricating a field effect transistors (FET) having an elevated source/drain structure. These methods may comprise the steps of: providing a integrated circuit substrate having a surface and a gate on the integrated circuit substrate; subsequently removing portions of the integrated circuit substrate to form a pair of recessed regions below the surface of the integrated circuit substrate, the recessed region being defined by a floor and sidewall in the integrated circuit substrate; and epitaxially growing a layer on the floor and sidewall of each recessed region.