Flat-cell nonvolatile semiconductor memory

Abstract

A flat-cell nonvolatile semiconductor memory. The semiconductor memory includes a plurality of units. Each unit includes word lines, a main bit line, a ground line, sub-bit lines, memory cell columns, and bank-selecting switches. Word lines are disposed in parallel, and the main bit line and the ground line cross the word lines. Sub-bit lines are disposed substantially in parallel to the main bit lines. Each memory cell column includes a plurality of memory cells connected in parallel between respective adjacent two of the sub-bit lines. The bank-selecting switches are used to select one of the memory cell columns. The first one of the bank-selecting switches is disposed between the main bit line and the fourth sub-bit line. The second of the bank-selecting switches is disposed between the main bit line and the second sub-bit line. The third of the bank-selecting switches is disposed between the ground line and the fifth sub-bit line. The fourth of the bank-selecting switches is disposed between the ground line and the third sub-bit line. The fifth of the bank-selecting switch is disposed between the ground line and the third sub-bit line. The sixth bank-selecting switch is disposed between the ground line and the first sub-bit line. Wherein, the second, third, and fourth bank-selecting switches are controlled by a first selecting signal, and the first, fifth, and sixth bank-selecting switches are controlled by a second selecting signal.