Memory array architectures based on a triple-polysilicon source-side injection non-volatile memory cell

Abstract

A semiconductor memory includes a plurality of memory cells arranged along rows and columns, each cell having a floating gate, a drain region, a source region, a program gate terminal, and a select gate terminal. The program gate terminals of the cells along each row of cells are connected together forming a continuous program gate line. The select gate terminals of the cells along each row of cells are connected together forming a continuous select gate line. The source regions of the cells along each row of cells are connected together forming a continuous source line. The cells along each column are divided into a predesignated number of groups, and the drain regions of the cells in each group are connected to a local bitline extending across the cells in the group of cells. A global bitline extends along every two columns of cells, and is configured to selectively provide electrical connection to the local bitlines along the corresponding two columns of cells. The floating gate of each cell is from a first layer polysilicon, the program gate lines are from a second polysilicon layer, the select gate lines are from a third polysilicon layer, and the source lines are diffusion lines.