The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 13, 2003
Filed:
Dec. 26, 2000
Hiroyuki Oi, Tokyo, JP;
Mitsubishi Materials Silicon Corporation, Tokyo, JP;
Abstract
In a photolithography process in which a resist film having window is provided on the surface of silicon wafer during the production of a dielectric isolated wafer, after coating back surface resist onto silicon wafer, its entire surface is exposed to light to crosslink the entire back surface resist. Consequently, during development and rinsing to avoid flooding of window by back surface resist that has moved around to the front side of the wafer following coating of back surface resist, dissolving of the periphery of back surface resist by that developing solution can be prevented. In addition, after polishing the surface of a dielectric isolated wafer on which dielectric isolated silicon island is formed, low-temperature polysilicon is deposited by CVD, or SOG is coated and baked, onto the surface of the dielectric isolated wafer. As a result, depression that has formed during surface polishing of the dielectric isolated wafer is filled in by low-temperature polysilicon layer or the SOG layer. Next, this low-temperature polysilicon layer or SOG layer is removed from the surface by polishing. At this time, the filled in portion of depression on the wafer surface remains. As a result, the surface of the dielectric isolated wafer can be flattened.