The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 13, 2003
Filed:
Dec. 05, 2000
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
An apparatus and method for providing delamination-resistant, array type molding of chip laminate packages such that larger chip array block sizes may be employed. An advanced mold die provides multiple wells for the formation of ejector pin tabs to be formed integrally to the mold cap of a chip laminate package. The die further provides for an ejector pin hole to be located at each ejector pin tab such that the ejector pins, when pressed for release of the laminate package from the mold die, bear against the integrally formed pin tabs rather than against the substrate of the chip/substrate assembly. The placement of the ejector pins for bearing against the pin tabs precludes the loading of the interface within the laminate package between the mold cap and the chip/substrate assembly. Substantially reduced delamination of the chip laminate package is achieved allowing for the use of larger chip array block sizes and providing for a substantial reduction in chip laminate package moisture sensitivity.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile