Power down voltage control method and apparatus

Abstract

A semiconductor device is provided for controlling entry to and exit from a power down (DPD) mode of a semiconductor memory comprising; a plurality of voltage generators for providing operating voltages to the semiconductor memory; a DPD controller for detecting a DPD condition and generating a DPD signal to control the application of the operating voltages to the semiconductor memory; and biasing circuitry for biasing a plurality of nodes of at least one of the plurality of voltage generators to at least one predetermined voltage potential to prevent false triggering of circuits upon entry/exit of DPD mode. Also provided is a semiconductor device, comprising: a plurality of input buffers for buffering a plurality of DPD-type signals for signaling a power down (DPD) condition including a DPD enter/exit signal: an auxiliary buffer for separately buffering the DPD enter/exit signal; a plurality of voltage generators for supplying operating voltages to internal circuit; DPD control circuit for receiving the DPD-type signals to decode DPD enter and exit commands and for outputting a voltage generator control signal to turn off the voltage generators when DPD enter command is decoded, and to turn off the plurality of buffers excluding the auxiliary buffer; and an auto-pulse generator for generating a voltage pulse upon receiving the DPD exit command to initialize internal circuits of the semiconductor device.