The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 2003

Filed:

Oct. 19, 2000
Applicant:
Inventors:

William R. McKee, Plano, TX (US);

Jiong-Ping Lu, Dallas, TX (US);

Ming-Jang Hwang, Dallas, TX (US);

Dirk N. Anderson, Plano, TX (US);

Wei Lee, Plano, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/144 ;
U.S. Cl.
CPC ...
H01L 2/144 ;
Abstract

A conducting plug/contact structure for use with integrated circuit includes a tungsten conducting plug formed in the via with a tungsten-silicon-nitride (WSi N ) region providing the interface between the tungsten conducting plug and the substrate (silicon) layer. The interface region is formed providing a nitrided surface layer over the exposed dielectric surfaces and the exposed substrate surface (i.e., exposed by a via in the dielectric layer) prior to the formation of tungsten/tungsten nitride layer filling the via. The structure is annealed forming a tungsten conducting plug with a tungsten-silicon-nitride interface between the conducting plug and the substrate. According to another embodiment, a tungsten nitride surface layer is formed over the nitrided surface layer prior to the formation of a tungsten layer to fill the via. According to another embodiment, a silicon surface layer is applied to the exposed surface of the dielectric layer and to the exposed surface of the substrate prior to formation of the nitrided surface layer. A layer of tungsten, tungsten/tungsten nitride, or tungsten nitride is formed to fill the via. After annealing, a tungsten conducting plug is formed with a tungsten-silicon-nitride interface region with the substrate.


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