Non-volatile semiconductor memory device having word line defect check circuit

Abstract

Disclosed is a non-volatile semiconductor memory device provided therein.with a word line defect check circuit. The non-volatile semiconductor memory device includes: a memory cell array including a plurality of cell array blocks including a plurality of cell strings that consist of floating gate memory cell transistors that its drain-source channels are in series connected each other between string select transistors and ground select transistors and that its control gates are correspondingly connected to a plurality of word lines, and a word line short check circuit that inputs different levels of voltage to each of the plurality of word lines that is adjacent from one another during a predetermined charging time, and that generates a short sense signal that indicates whether short between adjacent word lines is occurred by checking voltage levels of the word lines that were supplied with a same level of voltage, after the charging time is lapsed by a predetermined time.