The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6541860 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 01, 2003

Filed:

Jun. 05, 2001
Applicant:
Inventors:

Christy Mei-Chu Woo, Cupertino, CA (US);

Pin-Chin Connie Wang, Menlo Park, CA (US);

Joffre F. Bernard, Redwood City, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/348 ;
U.S. Cl.
CPC ...
H01L 2/348 ;
Abstract

An integrated circuit and a method for manufacture thereof are provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. An opening is formed in the dielectric layer. A barrier layer with an alloying element is deposited to line the opening in the dielectric layer. A conductor core is deposited on the barrier layer to fill the opening and connect to the semiconductor device. The conductor core is annealed causing migration of the alloy element into the conductor core.


Find Patent Forward Citations

Woo, Christy Mei-Chu. (2003). Barrier-to-seed layer alloying in integrated circuit interconnects (U.S. Patent No. 6541860). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6541860

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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