The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 01, 2003

Filed:

Jun. 27, 2001
Applicant:
Inventors:

Mark T. Ramsbey, Sunnyvale, CA (US);

Jean Y. Yang, Sunnyvale, CA (US);

Hidehiko Shiraiwa, San Jose, CA (US);

Michael A. Van Buskirk, Saratoga, CA (US);

David M. Rogers, Sunnyvale, CA (US);

Ravi S. Sunkavalli, Santa Clara, CA (US);

Janet S. Wang, San Francisco, CA (US);

Narbeh Derhacobian, Belmont, CA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/9792 ;
U.S. Cl.
CPC ...
H01L 2/9792 ;
Abstract

One aspect of the present invention relates to a non-volatile semiconductor memory device, containing a substrate, the substrate having a core region and a periphery region; a charge trapping dielectric over the core region of the substrate; a gate dielectric in the periphery region of the substrate; buried bitlines under the charge trapping dielectric in the core region; and wordlines over the charge trapping dielectric in the core region, wherein the core region is substantially planar.


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