The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2003

Filed:

Dec. 04, 2001
Applicant:
Inventors:

Hung-Sui Lin, Hsin-Ying, TW;

Han-Chao Lai, Taichung, TW;

Tao-Cheng Lu, Kaoshiung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/18247 ;
U.S. Cl.
CPC ...
H01L 2/18247 ;
Abstract

A method of fabricating a non-volatile memory, in which a charge-trapping layer consisting of insulating materials and bar-like conductive layers to be patterned into the gates are formed at first. The buried bit-lines are formed in the substrate between the bar-like conductive layers. Each of the buried bit-lines extends into the substrate under a portion of an adjacent high-K spacer, but not to the substrate under an adjacent bar-like conductive layer. High-K spacers are formed on the side-walls of the bar-like conductive layers. Then the bar-like conductive layers are patterned into the gates, and word-lines are formed on the substrate to electrically connect with the gates. The material of the high-K spacer has a dielectric constant and the high-K spacer has a width, such that a channel will extend to the substrate under the high-K spacer and connect with the buried bit-line when the non-volatile memory is operated.


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