The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2003

Filed:

Dec. 12, 2001
Applicant:
Inventors:

Heung Kyu Kwon, Seongnam, KR;

Tae Je Cho, Asan, KR;

Young Hoon Ro, Cheonan, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/312 ; H01L 2/352 ;
U.S. Cl.
CPC ...
H01L 2/312 ; H01L 2/352 ;
Abstract

A semiconductor package includes: a substrate having an upper surface and a lower surface; an integrated circuit chip having bond pads; a lid attached on the upper surface of the substrate so as to cover the chip; and one or more projections that electrically connect the lid to a plurality of ground patterns. The substrate has substrate pads formed on the upper surface, and one or more of the substrate pads extend to form the ground patterns. The chip is bonded on the upper surface of the substrate. One or more of the bond pads are ground bond pads, and the bond pads are electrically connected to the corresponding substrate pads. An electrically nonconductive adhesive is used for the attachment of the lid to the substrate, and the projections are connected to the ground patterns by an electrically conductive adhesive. The ground projections are positioned at four corners of a cavity that is formed between the substrate and the lid. The semiconductor package further includes: external connection terminals formed on the lower surface of the substrate and electrically connected to the corresponding substrate pads; and a thermal interface material is interposed between lid and the chip, the thermal interface material transmitting heat generated by the chip to the lid.


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