The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 11, 2003
Filed:
Mar. 11, 2002
Geum-Jong Bae, Suwon, KR;
Sang-Su Kim, Kyunggi-do, KR;
Tae-Hee Choe, Seoul, KR;
Hwa-Sung Rhee, Seoul, KR;
Abstract
In an SOI-type semiconductor device and a method of forming the same a semiconductor device is formed in an SOI-type substrate that is composed of a lower silicon layer, a buried oxide layer, and an SOI layer. The SOI substrate includes a device region isolated by a device isolation layer and the buried oxide layer, in which a source/drain region for forming at least one MOSFET at a body composed of the SOI layer is formed; and a ground region which is isolated from the device region by the device isolation layer and is composed of the body. A bottom portion of the device isolation layer is separated from the buried oxide layer by a connecting portion that electrically connects a body of the device region to a body of the ground region through the SOI layer. A silicon germanium layer is formed in the SOI layer, and at least partially remains at the SOI layer connecting the body of the device region to the body of the ground region in the connecting portion. Preferably, the device isolation layer is a trench-type isolation layer. The silicon germanium layer is formed at an interface between the SOI layer and the lowest portion of the SOI layer, i.e., a buried oxide layer, or is sandwiched between silicon layers that constitute the SOI layer under the SOI layer.