Pattern generator for semiconductor test system

Abstract

A pattern generator for generating a test pattern that has a repetition rate higher than the basic repetition rate thereof to test a synchronous memory. The test pattern to be provided to a memory under test can be accurately modified by inverting the pattern data as a function of address data. The pattern generator includes an address generator for generating an address signal with a test rate T to be supplied to a memory under test, a data generator for generating write data to be stored in the memory under test wherein the data generator is formed of a first data generator for generating even number write data, a second data generator for generating odd number write data, an address converter provided with the address signal for generating an even number address incrementing by two at each test rate T and an odd number address incrementing by two at each test rate T, first means for inverting the even number data from the first data generator as a function of the even number address, and second means for inverting the odd number data from the second data generator as a function of the odd number address.