The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2003

Filed:

Mar. 18, 2002
Applicant:
Inventors:

Teng-Feng Wang, Chang-Hwa Hsien, TW;

Lung Chen, Hsinchu, TW;

Chen-Chiu Hsue, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/1336 ;
Abstract

A method for manufacturing a MOS device with improved well control stability. The method includes the steps of providing a semiconductor substrate; forming a gate electrode according to a critical dimension on the semiconductor substrate, wherein the gate electrode comprises a gate oxide layer and a conducting gate; inspecting a real dimension of the conducting gate; determining a thickness of subsequently formed conducting gate spacers according to the real dimension of the conducting gate, such that variations of electric characteristics of the device affected by the critical dimension of the conducting gate are reduced; and forming the conducting gate spacers with the determined thickness on sidewalls of the gate electrode.


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