Multi-condition bisr test mode for memories with redundancy

Abstract

A memory device configured to detect changes in fault patterns is disclosed. In one embodiment, the memory device includes a memory array, a built-in self-test (BIST) unit, and a built-in self-repair (BISR) unit. The BIST unit runs test patterns on the memory array to identify faulty locations in the array. A comparator within the BIST or external to the BIST compares the actual output of the memory array to the expected output, and asserts an error signal whenever a mismatch occurs. The BISR unit intercepts addresses directed to the memory array, and operates on the addresses in three distinct phases. During a training phase, the BISR unit stores the intercepted addresses when the error signal is asserted. During the normal operation phase, the BISR unit compares all intercepted addresses to stored addresses and redirects a corresponding memory access if any intercepted address matches a stored address. During a verification phase, the BISR unit compares intercepted addresses designated by assertions of the error signal to the addresses previously stored in the training phase. If the faulty intercepted address fails to match a stored address, the BISR unit asserts a “new error” signal. If at the end of the verification phase, a stored address has not matched nay intercepted faulty address, the BISR asserts a “missed error” signal.