The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2003

Filed:

Mar. 13, 2001
Applicant:
Inventors:

Chin-Lai Chen, Taoyuan Hsien, TW;

Tony Lin, Kaohsiung Hsien, TW;

Jih-Wen Chou, Hsin-Chu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/1336 ;
Abstract

A MOS transistor includes a substrate, an insulation layer, a gate and a dielectric layer. The substrate includes a drain and a source separately positioned on the surface of the substrate. The insulation layer is positioned on the surface of the substrate between the drain and the source. The gate includes a conducting layer positioned on the insulation layer having a bottom side, a top side, a left side and a right side, and a metallic silicide layer positioned on the top side of the conducting layer wherein the width of the metallic silicide layer is greater than that of the bottom side of the conducting layer. The dielectric layer covers the drain, the source and the metallic silicide layer. The transistor includes at least one empty side slot positioned between the dielectric layer and the left side or right side of the conducting layer below the metallic silicide layer.


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