The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 07, 2003
Filed:
Jan. 23, 2001
Hiromi Todorobaru, Kashiwa, JP;
Hideo Miura, Koshigaya, JP;
Masayuki Suzuki, Kokubunji, JP;
Shinji Nishihara, Koganei, JP;
Shuji Ikeda, Koganei, JP;
Masashi Sahara, Kodaira, JP;
Shinichi Ishida, Higashimurayama, JP;
Hiromi Abe, Tokyo, JP;
Atushi Ogishima, Tachikawa, JP;
Hiroyuki Uchiyama, Higashimurayama, JP;
Sonoko Abe, Higashimurayama, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
Disclosed is a method of fabricating a semiconductor device including forming an insulating film on a silicon substrate; forming a contact hole in the insulating film; depositing a titanium film to be in contact with the silicon substrate in the contact hole; and causing a heat reaction between the titanium film and the silicon substrate such that the titanium film is subjected to silicide reaction with the thickness 4 nm to 48 nm or, more preferably, with the thickness of 8 nm to 34 nm. In the instance where the contact hole is filled with doped polycrystal silicon material, the titanium film is deposited to be in contact with the polycrystal silicon in the contact hole. The silicon substrate/silicon body may have at least a MISFET formed thereon in which case the contact hole is formed to expose an active region of the MISFET, as one example.