Dual-chip integrated circuit package with unaligned chip arrangement and method of manufacturing the same

Abstract

A dual-chip integrated circuit package with unaligned chip arrangement and a method of manufacturing such a dual-chip integrated circuit package are provided. The dual-chip integrated circuit package includes a leadframe having a first set of leads and a second set of leads. The dual-chip integrated circuit package is used to pack two integrated circuit chips in an unaligned chip arrangement, in which the first integrated circuit chip is mounted to one side of the inner part of the first set of leads, and the second integrated circuit chip is mounted to the other side of the same in such a manner as to allow the bonding pads on the second integrated circuit chip to be positioned in the spacing formed between the two sets of leads. This unaligned chip arrangement can help facilitate the wire-bonding process for the bonding pads are the second integrated circuit chip. An encapsulant is used for encapsulating the first integrated circuit chip, the second integrated circuit chip, the set of bonding wires, the second set of bonding wires, the inner part of the first set of leads, and the inner part of the second set of leads. The particular structure of the dual-chip integrated circuit package allows no restriction to the relative size between first two integrated circuit chips, thus allowing flexible selection for the combination of the two integrated circuit chips. Moreover, the dual-chip integrated circuit package are help save layout space on the circuit board and offers more functionality and storage capacity.