The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2002

Filed:

Mar. 26, 2001
Applicant:
Inventors:

Shuuichi Ueno, Tokyo, JP;

Katsuyuki Horita, Tokyo, JP;

Takashi Kuroi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1425 ;
U.S. Cl.
CPC ...
H01L 2/1425 ;
Abstract

Provided are a semiconductor device having a MOS transistor of a structure capable of obtaining a good characteristic particularly about assurance of resistance to punch-through and leak current reduction, as well as a method of manufacturing the same. That is, in addition to the usual MOS transistor structure, a channel dope region ( ) is disposed at a predetermined depth so as to extend substantially the entire surface of a flat surface in a P well region ( ) including a channel region. In the channel dope region ( ), it is set so that the maximum value of the P type impurity concentration (MAX of P) ranges from 1×10 to 1×10 , and the maximum value of the N type impurity concentration (MAX of N) of a source/drain region ( ( )) is not less than 10% and not more than 100%. Note that the surface proximate region of the P well region ( ) is to be beyond the object.


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