The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 17, 2002
Filed:
Feb. 28, 2001
Shan Sun, Colorado Springs, CO (US);
George Hickert, Colorado Springs, CO (US);
Diana Johnson, Colorado Springs, CO (US);
John Ortega, Colorado Springs, CO (US);
Eric Dale, Colorado Springs, CO (US);
Masahisa Ueda, Suyama Susono, JP;
Other;
Abstract
A method for fabricating integrated capacitors, of particular utility in forming a ferroelectric capacitor array for a ferroelectric memory integrated circuits, begins with provision of a substrate. The substrate is typically a partially-processed CMOS integrated circuit wafer coated with an adhesion layer. Upon the substrate is deposited a bottom electrode layer, typically of noble metal, a dielectric layer, typically doped PZT, and a top electrode layer, typically a noble metal oxide. Next is deposited a hardmask layer of strontium ruthenium oxide, followed by a photoresist layer. The photoresist layer is aligned, exposed, developed, and cured as known in the art of integrated circuit photolithography. The resulting stack is then dry etched to remove undesired portions of the hardmask layer, the top electrode layer, and the dielectric layer. A principle advantage of the process is that a single photomasking operation is sufficient to define the top electrode and dielectric layers.