The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2002

Filed:

Mar. 16, 2000
Applicant:
Inventors:

Arne W. Ballantine, Cold Spring, NY (US);

Peter A. Emmi, Hyoe Park, NY (US);

Walter J. Frey, Waterbury Center, VT (US);

Michael J. Gambero, Colchester, VT (US);

Neena Garg, Fishkill, NY (US);

Byeongju Park, Wappingers Falls, NY (US);

Donald L. Wilson, New Windsor, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C23C 1/600 ; B65H 1/00 ; B65G 1/133 ;
U.S. Cl.
CPC ...
C23C 1/600 ; B65H 1/00 ; B65G 1/133 ;
Abstract

An apparatus and method for controlling wafer temperature and environment is provided. The apparatus includes a batch processing fixture for batch processing wafers at a first elevated temperature. The batch of wafers is not substantially ramped in temperature within the batch processing fixture. The apparatus also includes a single wafer processing apparatus for rapidly ramping temperature of a wafer of the batch from the first elevated temperature wherein a uniform temperature across the wafer is maintained during the ramping. Another embodiment of the apparatus ( ) includes an RTP chamber ( ) having an inert or reducing environment and that includes a pedestal ( ) for holding a single wafer ( ) and a heater unit ( ) arranged so as to uniformly and rapidly heat the single wafer. The apparatus also includes a cooling chamber ( ) having an inert or reducing environment and located adjacent the RTP chamber and selectively open thereto, and includes a pedestal ( ) for holding the single wafer, a first loading chamber ( ) having an inert or reducing environment and located adjacent the cooling chamber and selectively opened thereto, and having a cassette ( ) for holding one or more wafers. The apparatus also includes a thermal processing chamber ( ), such as an LPCVD furnace, located adjacent the loading chamber and arranged to receive the cassette so as to perform a thermal process of the wafers in the cassette.


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