The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2002

Filed:

Apr. 24, 1998
Applicant:
Inventors:

Takuya Fukuda, Kodaira, JP;

Nobuyoshi Kobayashi, Kawagoe, JP;

Yoshitaka Nakamura, Oume, JP;

Masayoshi Saito, Hachiouji, JP;

Shinichi Fukada, Hino, JP;

Yoshifumi Kawamoto, Tsukui-gun, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/348 ; H01L 2/940 ; H01L 2/7108 ; H01L 2/976 ; H01L 3/1119 ;
U.S. Cl.
CPC ...
H01L 2/348 ; H01L 2/940 ; H01L 2/7108 ; H01L 2/976 ; H01L 3/1119 ;
Abstract

The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.


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