The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2002

Filed:

Sep. 15, 1999
Applicant:
Inventors:

Ryuji Kono, Ibaraki-ken, JP;

Akihiko Ariga, Musashimurayama, JP;

Hideyuki Aoki, Takasaki, JP;

Hiroyuki Ohta, Tsuchiura, JP;

Yoshishige Endo, Tsuchiura, JP;

Masatoshi Kanamaru, Ibaraki-ken, JP;

Atsushi Hosogane, Ibaraki-ken, JP;

Shinji Tanaka, Ushiku, JP;

Naoto Ban, Sagamihara, JP;

Hideo Miura, Koshigaya, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/166 ;
U.S. Cl.
CPC ...
H01L 2/166 ;
Abstract

Semiconductor device chips manufacturing and inspecting method is disclosed in which a semiconductor wafer is cut into individual LSI chips. The LSI chips are rearranged and integrated into a predetermined number. The cut LSI chips are integrated in a jig having openings with a size commensurate with the dimensions of the LSI chip. At least one part of the jig having such openings has a coefficient of thermal expansion that is approximately equal to that of the LSI chips. The integrated predetermined number of chips are subjected to an inspection process in a subsequent inspection step thereby improving efficiency and reducing cost.


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