The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 05, 2002
Filed:
Jan. 31, 2001
Applicant:
Inventors:
Franz Hofmann, München, DE;
Wolfgang Krautschneider, Hohenthann, DE;
Josef Willer, Riemerling, DE;
Assignee:
Siemens Aktiengesellschaft, Munich, DE;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ; H01L 2/18234 ; H01L 2/18236 ; H01L 2/976 ; H01L 2/994 ;
U.S. Cl.
CPC ...
H01L 2/1336 ; H01L 2/18234 ; H01L 2/18236 ; H01L 2/976 ; H01L 2/994 ;
Abstract
A method for production of a memory cell arrangement which includes vertical MOS transistors as memory cells, wherein the information is stored utilizing at least three different threshold voltage values of the transistors by multi-level programming. One threshold voltage value is realised by the thickness of the gate dielectric in the sense of a thick oxide transistor and the other threshold voltage values are realised by different channel dopings. The arrangement can be produced with as area requirement for each memory cell of 2 F (F: minimum structure size).