The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2002

Filed:

Mar. 14, 2000
Applicant:
Inventors:

Andres Bryant, Essex Junction, VT (US);

William F. Clark, Jr., Essex Junction, VT (US);

Edward J. Nowak, Essex Junction, VT (US);

Minh H. Tong, Essex, VT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/162 ;
U.S. Cl.
CPC ...
H01L 2/162 ;
Abstract

A decoupling capacitor and methods for forming the same are provided. In a first aspect, the decoupling capacitor is formed during a process for forming first and second type FETs on a common substrate that comprises a plurality of implant steps for doping channels and diffusions of the first and second type FETs. In a second aspect, a method is provided for forming the novel decoupling capacitor that includes the steps of forming a mandrel layer on a substrate, including forming openings in the mandrel layer and disposing a first type dopant into the substrate through the openings. Thereafter, an epitaxial layer is formed in the openings on the substrate, an insulator layer is formed in the openings on the epitaxial layer and a gate is formed in the openings on the insulator layer. The mandrel layer is removed and the first type dopant is disposed into the substrate abutting the first type dopant in the substrate that was disposed through the openings. During this step the first type dopant is disposed into the gate. The substrate having the first type dopant comprises one terminal of the capacitor and the gate comprises another terminal of the capacitor.


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