The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2002

Filed:

Feb. 28, 2002
Applicant:
Inventors:

Guo-Ren Hu, Taipei, TW;

Ying-Chia Chen, Taichung, TW;

Chi-Wei Chao, Taipei, TW;

Yew-Chung Wu, Taichung, TW;

Yao-Lun Hsu, Taipei, TW;

Yuan-Tung Dai, Tao-Yuan, TW;

Wen-Tung Wang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/184 ; H01L 2/7148 ;
U.S. Cl.
CPC ...
H01L 2/184 ; H01L 2/7148 ;
Abstract

A method for forming a thin film transistor (TFT) is disclosed. The invention uses metal electroless plating or chemical displacement processes to form metal clusters adjacent the sidewall of amorphous silicon active region pattern so as to crystallize the amorphous silicon amid the subsequently performed metal induced lateral crystallization (MILC) process. The amorphous silicon is crystallized to form polysilicon having parallel grains. Since the amorphous silicon will crystallize with a specific angle which is measured between the grain orientation and the side wall of the amorphous silicon, a tilt channel connecting the source and drain region of the TFT is utilized to upgrade the electron mobility across the tilt channel, wherein the grain orientation of polysilicon in the tilt channel perpendicular to a gate electrode which is subsequently formed above the tilt channel.


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