Semiconductor memory device which can be simultaneously tested even when the number of semiconductor memory devices is large and semiconductor wafer on which the semiconductor memory devices are formed

Abstract

At the time of writing data, a tester outputs a chip enable signal /CE of the L level and selection signals of the L level to simultaneously make semiconductor memory devices active. At the time of reading data, the tester outputs the chip enable signal of the L level to the semiconductor memory devices, and selectively switches the logic level of a selection signal to be outputted to some semiconductor memory devices and that of the selection signal to be outputted to the other semiconductor memory devices to the L level. In such a manner, a number of semiconductor memory devices can be tested without increasing the number of pins of the tester.