The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 15, 2002
Filed:
Aug. 22, 2001
United Microelectronics Corp., Hsin-Chu, TW;
Abstract
An ESD protection device is formed on a P-type well, and has at least one NMOS, at least one first P diffusion region for electrically connecting to a P-well biasing circuit, at least one dummy gate between the NMOS and the first P diffusion region, at least one second P diffusion region for electrically connecting to a V power terminal, and at least one shallow trench isolation (STI) structure for isolating the NMOS and the second P diffusion region. A drain of the NMOS, the P-type well, and a source of the NMOS form a parasitic lateral n-p-n bipolar junction transistor (BJT), and the drain and the source of the NMOS are electrically connected to an I/O buffering pad and a V power terminal respectively. When an ESD voltage pulse zaps the I/O buffering pad, the P-well biasing circuit induces a substrate trigger current (I ), causing the parasitic lateral n-p-n BJT to trigger on and quickly discharge a current incurred from the ESD voltage pulse.