The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2002

Filed:

Nov. 28, 2000
Applicant:
Inventors:

Mark T. Ramsbey, Sunnyvale, CA (US);

Jean Y. Yang, Sunnyvale, CA (US);

Hidehiko Shiraiwa, San Jose, CA (US);

Michael A. Van Buskirk, Saratoga, CA (US);

David M. Rogers, Sunnyvale, CA (US);

Ravi Sunkavalli, Santa Clara, CA (US);

Janet Wang, San Francisco, CA (US);

Narbeh Derhacobian, Belmont, CA (US);

Yider Wu, San Jose, CA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/1336 ;
Abstract

One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region.


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