The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 08, 2002
Filed:
May. 31, 2001
Applicant:
Inventors:
Ivan Pavisic, San Jose, CA (US);
Pedja Raspopovic, Cupertino, CA (US);
Aiguo Lu, Cupertino, CA (US);
Assignee:
LSI Logic Corporation, Milpitas, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/45 ; G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 9/45 ; G06F 1/750 ;
Abstract
True paths are identified in a timing graph of a circuit in which the timing graph contains known false paths containing nodes of at least two sets selected from FROM, THROUGH and TO nodes. The false paths are processed to include sets of FROM and TO nodes and then transformed into equivalent sets of two logical false paths. True path intervals are constructed as logical subgraphs that do not describe any equivalent false path. In preferred embodiments, the process is carried out by a computer under control of a computer readable program.