The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 01, 2002
Filed:
Dec. 22, 1999
Edward O. Travis, Austin, TX (US);
Sejal N. Chheda, Austin, TX (US);
Bradley P. Smith, Austin, TX (US);
Ruiqi Tian, Pflugerville, TX (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
At least one process-assist feature ( ) at or near a via location of a wiring structure ( ) within a semiconductor device is used to improve processing or processing margin during subsequent processing. For at least some of the embodiments of the present invention, the process-assist features feature ( ) help to make a flowable layer more uniform over via locations ( ). Typically, this can help in the formation of via openings. When a resist layer ( ) is formed over the process-assist features, the resist layer ( ) will have a more uniform thickness over most via locations within the device. When an insulating layer ( ) is formed over the via locations, the insulating layer ( ) will have a more uniform thickness over most via locations within the device. More control during resist exposure or via opening etching allow more process margin. The embodiments described herein illustrate the flexibility in placing process-assist features.