The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2002

Filed:

Sep. 12, 2000
Applicant:
Inventors:

Wen-Kuan Yeh, Chupei, TW;

Jih-Wen Chou, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1425 ;
U.S. Cl.
CPC ...
H01L 2/1425 ;
Abstract

A method for fabricating a metal-oxide semiconductor (MOS) transistor. A substrate having a gate structure is provided. The method of the invention includes forming a liner spacer on each side of the gate structure and a low dopant density region deep inside the substrate. The low dopant density region has a lower dopant density than that of a lightly doped region of the MOS transistor. Then a interchangeable source/drain region with a lightly doped drain (LDD) structure and an anti-punch-through region is formed on each side of the gate structure in the low dopant density region. The depth of the interchangeable source/drain region is not necessary to be shallow.


Find Patent Forward Citations

Yeh, Wen-Kuan. (2002). Semiconductor device having varied dopant density regions (U.S. Patent No. 6451675). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6451675

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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