The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 03, 2002
Filed:
Jan. 18, 2001
Applicant:
Inventors:
Hiroshi Matsuo, Hyogo, JP;
Yuichi Yokoyama, Hyogo, JP;
Takuji Oda, Hyogo, JP;
Kiyoshi Maeda, Hyogo, JP;
Shinya Inoue, Hyogo, JP;
Yuji Yamamoto, Hyogo, JP;
Assignee:
Other;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/18238 ;
U.S. Cl.
CPC ...
H01L 2/18238 ;
Abstract
A hard mask insulating layer is formed on a gate electrode which is formed on a main surface of a silicon substrate with a gate insulating layer interposed. An SiN sidewall spacer is directly formed on a thin SiO layer which is formed to cover a side surface of the gate electrode. A contact hole is formed to penetrate an interlayer insulating layer formed on an SiN stopper layer and reach the main surface of the silicon substrate.
Quick Actions:
Matsuo, Hiroshi. (2002). Method of fabricating a semiconductor device (U.S. Patent No. 6444515). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6444515
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile